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1 ? fn6828.2 isl9103, isl9103a 500ma 2.4mhz low i q high efficiency synchronous buck converter the isl9103, isl9103a is a 500ma, 2.4mhz step-down regulator, which is ideal for powering low-voltage microprocessors in compact devices such as pdas and cellular phones. it is optimized for generating low output voltages down to 0.8v. the supply voltage range is from 2.7v to 6v allowing the use of a single li+ cell, three nimh cells or a regulated 5v input. it has guaranteed minimum output current of 500ma. a high switching frequency of 2.4mhz pulse-width modulation (pwm) allows using small external components. under light load condition, the device operates at low i q skip mode with typical 20a quiescent current for highest light load efficiency to maximize battery life, and it automatically swit ches to fixed frequency pwm mode under heavy load condition. the isl9103, isl9103a includes a pair of low on-resistance p-channel and n-channel internal mosfets to maximize system efficiency and minimize the external component count. 100% duty- cycle operation allows less than 300mv dropout voltage at 500ma. the isl9103, isl9103a offers internal digital soft-start, enable for power sequence, overcurrent protection and thermal shutdown functions. in addition, the isl9103, isl9103a offers a quick bleeding function that discharges the output capacitor when the ic is disabled. the isl9103, isl9103a is offered in a 1.6x1.6mm tdfn package. the complete converter occupies less than 0.5cm 2 . pinout isl9103, isl9103a (6 ld 1.6x1.6 tdfn) top view features ? high efficiency integrated synchronous buck regulator with up to 95% efficiency ? 2.7v to 6.0v supply voltage ? 2.4mhz pwm switching frequency ? 500ma guaranteed output current ? 3% output accuracy over-temperature and line for fixed output options ? 20a quiescent supply current in skip mode ? less than 1a logic controlled shutdown current ? 100% maximum duty cycle for lowest dropout ? ultrasonic switching frequency at skip mode to prevent audible frequency noise (for isl9103a only) ? discharge output capacitor when disabled ? internal digital soft-start ? peak current limiting, short circuit protection ? over-temperat ure protection ? chip enable ? small 6 pin 1.6mmx1.6mm tdfn package ? pb-free (rohs compliant) applications ? single li-ion battery-powered equipment ? mobile phones and mp3 players ? pdas and palmtops ?wcdma handsets ? portable instruments 1 2 3 6 4 5 vin en nc sw gnd fb data sheet november 24, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6828.2 november 24, 2009 pin descriptions pin number pin name description 1vin input supply voltage. typically connect a 10f ceramic capacitor to ground. 2en regulator enable pin. enable the device when driven to high. shut down the chip and discharge output capacitor when driven to low. do not leave this pin floating. 3nc no connect; leave floating. 4fb buck converter output feedback pin. for adju stable output version, its typical value is 0.8v and connect it to the output through a resistor divider for desired output voltage; for fixed output version, directly connect this pin to the converter output. 5gnd ground connection. 6sw switching node connection. connect to one terminal of inductor. ordering information part number (notes 1, 3, 4) part marking output voltage (v) (note 2) temp range (c) package tape and reel (pb-free) pkg dwg. # ultrasonic function isl9103irunz-t j0 3.3 -40 to +85 6 ld tdfn l6.1.6x1.6 no isl9103irujz-t j1 2.8 -40 to +85 6 ld tdfn l6.1.6x1.6 no isl9103irufz-t j2 2.5 -40 to +85 6 ld tdfn l6.1.6x1.6 no isl9103irudz-t j3 2.0 -40 to +85 6 ld tdfn l6.1.6x1.6 no isl9103irucz-t j4 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6 no isl9103irubz-t j5 1.5 -40 to +85 6 ld tdfn l6.1.6x1.6 no isl9103iruwz-t j6 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6 no ISL9103IRUAZ-T j7 adj -40 to +85 6 ld tdfn l6.1.6x1.6 no isl9103airunz-t j8 3.3 -40 to +85 6 ld tdfn l6.1.6x1.6 yes isl9103airujz-t j9 2.8 -40 to +85 6 ld tdfn l6.1.6x1.6 yes isl9103airufz-t k0 2.5 -40 to +85 6 ld tdfn l6.1.6x1.6 yes isl9103airudz-t k1 2.0 -40 to +85 6 ld tdfn l6.1.6x1.6 yes isl9103airucz-t k2 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6 yes isl9103airubz-t k3 1.5 -40 to +85 6 ld tdfn l6.1.6x1.6 yes isl9103airuwz-t k4 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6 yes isl9103airuaz-t k5 adj -40 to +85 6 ld tdfn l6.1.6x1.6 yes notes: 1. please refer to tb347 for details on reel specifications. 2. other output voltage options may be available upon r equest, please contact intersil for more details. 3. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and comp atible with both snpb and pb-free soldering operations. intersi l pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl9103, isl9103a . for more information on msl please see techbrief tb363 . isl9103, isl9103a
3 fn6828.2 november 24, 2009 absolute maximum rati ngs thermal information vin, en to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v sw to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v fb to gnd (for adjustable version) . . . . . . . . . . . . . . . -0.3v to 2.7v fb to gnd (for fixed output version) . . . . . . . . . . . . . . -0.3v to 3.6v recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . 2.7v to 6.0v load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .up to 500ma ambient temperature range . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, note 5) ja (c/w) 6 ld 1.6x1.6 tdfn package . . . . . . . . . . . . . . . . . 160 junction temperature range. . . . . . . . . . . . . . . . . .-40c to +125c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 5. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are meas ured at the following conditions: t a = +25c, v in = v en = 3.6v, l = 2.2h, c 1 = 10f, c 2 = 10f, i out = 0a (see ?typical applications? on page 8). boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note6) typ max (note 6) units supply undervoltage lockout threshold (uvlo) v uvlo t a = +25c, rising - 2.5 2.7 v uvlo hysteresis 50 150 - mv quiescent supply current (for isl9103 adjustable output voltage only) i vin1 in skip mode, no load at the output, no switch, v in = 6.0v -20 34 a quiescent supply current (for isl9103a adjustable output only) i vin2 in skip mode, no load at the output, no switch, v in = 6.0v -32 45 a shut down supply current i sd v in = 6.0v, en = low - 0.05 1 a output regulation fb voltage accuracy (for adjustable output only) t a = 0c to +85c -2 - +2 % -2.5 - +2.5 % fb voltage v fb 0.8 v fb bias current (for adjustable output only) i fb vfb = 0.75v - 5 100 na output voltage accuracy (for fixed output voltage only) pwm mode -3 - 3 % line regulation v in = v o + 0.5v to 6v (minimal 2.7v) - 0.2 - %/v load regulation v in = 3.6v, i o = 150ma to 500ma - 0.0009 - %/ma sw p-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.45 0.6 v in = 2.7v, i o = 200ma - 0.55 0.72 n-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.4 0.52 v in = 2.7v, i o = 200ma - 0.5 0.65 n-channel bleeding mosfet on-resistance - 100 - p-channel mosfet peak current limit i pk v in = 4.2v 0.7 0.95 1.30 a maximum duty cycle - 100 - % sw leakage current sw at hi-z state - 0.01 2 a pwm switching frequency f s v in = 3.6v 1.9 2.4 2.75 mhz isl9103, isl9103a
4 fn6828.2 november 24, 2009 sw minimum on-time -65- ns soft-start-up time -1.2- ms en logic input low -- 0.4 v logic input high 1.4 --v logic input leakage current -0.1 1 a thermal shutdown - 130 - c thermal shutdown hysteresis -30-c note: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested electrical specifications unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are meas ured at the following conditions: t a = +25c, v in = v en = 3.6v, l = 2.2h, c 1 = 10f, c 2 = 10f, i out = 0a (see ?typical applications? on page 8). boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note6) typ max (note 6) units typical operating performance figure 1. efficiency vs load current (vo = 1.5v) f igure 2. efficiency vs load current (vo = 2.5v) figure 3. input quiescent current vs v in (vo = 2.5v) figure 4. output voltage vs load current (isl9103, vo_norminal = 1.8v) 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 i o (a) efficiency (%) v in = 3.8v v in = 2.7v v in = 4.9v 0 10 20 30 40 50 60 70 80 90 100 0 0.10.20.30.40.5 i o (a) efficiency (%) v in = 3.5v v in = 4.5v v in = 5.5v 10 15 20 25 30 2.70 3.25 3.80 4.35 4.90 5.45 6.00 v in (v) iq (a) t = +85c t = +25c t = -45c 1.775 1.780 1.785 1.790 1.795 1.800 0 100 200 300 400 500 i out (ma) v o (v) vin = 3.6v, falling vin = 3.6v, rising isl9103, isl9103a
5 fn6828.2 november 24, 2009 figure 5. output voltage vs load current (isl9103, vo_norminal = 2.5v) figure 6. soft-start to pfm mode (v in = 3.6v, v out = 1.5v, i out = 0.001ma) figure 7. soft-start to pwm mode (v in = 3.6v, v out = 1.5v, i out = 500ma) figure 8. soft-start to pfm mode (v in = 3.6v, v out = 2.5v, i out = 0.001ma) figure 9. load transient in pfm mode (v in = 3.6v, v out = 1.5v, 5ma to 30ma) figure 10. load transient in pfm mode (v in = 3.6v, v out = 1.5v, 30ma to 5ma) typical operating performance (continued) 2.495 2.500 2.505 2.510 2.520 0 100 200 300 400 500 i out (ma) v o (v) 2.515 vin = 4.0v, falling vin = 4.0v, rising v sw i l v out 5v/div 200ma/div 1v/div 5v/div en v sw i l v out 5v/div 500ma/div 1v/div 5v/div en v sw i l v out 5v/div 200ma/div 2v/div 5v/div en 5v/div 50mv/div 20ma/div v sw i o v out i o 5v/div 50mv/div 20ma/div v sw v out isl9103, isl9103a
6 fn6828.2 november 24, 2009 figure 11. load transient in pfm mode (v in = 3.6v, v out = 2.5v, 5ma to 30ma) figure 12. load transient in pfm mode (v in = 3.6v, v out = 2.5v, 30ma to 5ma) figure 13. load transient from pfm to pwm mode (v in = 3.6v, v out = 1.5v, 5ma to 300ma) figure 14. load transient from pwm to pfm mode (v in = 3.6v, v out = 1.5v, 300ma to 5ma) figure 15. load transient from pfm to pwm mode (v in = 3.6v, v out = 2.5v, 5ma to 300ma) figure 16. load transient from pwm to pfm mode (v in = 3.6v, v out = 2.5v, 300ma to 5ma) typical operating performance (continued) i l 5v/div 50mv/div 20ma/div v sw v out v sw i l v out 5v/div 50mv/div 20ma/div v sw i o v out 5v/div 200ma/div 50mv/div 5v/div 50mv/div 200ma/div v sw i o v out 5v/div 50mv/div 200ma/div v sw i l v out (ac coupled) v sw i l v out (ac coupled) 50mv/div 5v/div 200ma/div isl9103, isl9103a
7 fn6828.2 november 24, 2009 figure 17. load transient in pwm mode (v in = 3.6v, v o = 1.5v, 200ma to 500ma) figure 18. load transient in pwm mode (v in = 3.6v, v o = 1.5v, 500ma to 200ma) figure 19. load transient in pwm mode (v in = 3.6v, v o = 2.5v, 200ma to 500ma) figure 20. load transient in pwm mode (v in = 3.6v, v o = 2.5v, 500ma to 200ma) typical operating performance (continued) 5v/div 50mv/div 500ma/div v sw i o v out (ac coupled) 5v/div 50mv/div 500ma/div v sw i o v out v sw i o v out 5v/div 50mv/div 500ma/div v sw i o v out 5v/div 50mv/div 500ma/div isl9103, isl9103a
8 fn6828.2 november 24, 2009 typical applications figure 21. typical applications diagram note: for adjustable output version, the internal feedback resistor divider is disabled and the fb pin is directly connected to the error amplifier. c2 10f l sw gnd fb vin en input: 2.7v to 6v output up to 500ma c1 10 f isl9103, isl9103a fixed output 2.2h c2 10f l sw gnd fb vin en input: 2.7v to 6v output up to 500ma c1 10f isl9103, isl9103a adjustable output 2.2h r1 100k r2 100k c3 47pf enable disable enable disable table 1. bill of materials parts description manufacturers part number specifications size l inductor sumida cdrh2d14np-2r2nc 2.2h 3.2mmx3.2mm c1, c2 input and output capacitor panasonic ecj-1vb1a106m 10f/10v, x5r 0603 c3 capacitor kemet c0402c470j5gactu 47pf/50v 0402 r1, r2 resistor various - 100k , smd, 1% 0402 isl9103, isl9103a
9 fn6828.2 november 24, 2009 block diagram theory of operation the isl9103, isl9103a is a step-down switching regulator optimized for battery-powered handheld applications. the regulator operates at typical 2.4mhz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, the regulator can automatically enter the skip mo de (pfm mode) to reduce the switching frequency to minimize the switching loss and to maximize the battery life. the quiescent current under skip mode, and under no load and no s witch condition is typically only 20a. the supply current is typically only 0.05a when the regulator is disabled. pwm control scheme the isl9103, isl9103a uses the peak-current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting. figure 22 shows the circuit functional block diagram. the current loop consists of the oscillator, the pwm comparator comp, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current sense amplifier (csa). the control reference for the current loops comes from the error amplifier (eamp) of the voltage loop. the pwm operation is initiali zed by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and th e current in the p-channel mosfet starts ramping up. when the sum of the csa output and the compensation slope reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-channel mosfet and to turn on the n-channel mosfet. the n-mosfet remains on till the end of the pwm cycle. figure 23 shows the typical operating waveforms during the normal pwm operation. the dotted lines illu strate the sum of the slope compensation ramp and the csa output. sw + csa + + ocp vref1 skip + + x slope comp so ft sta rt soft- start vref eamp comp pwm/pfm logic controller protection driver fb shutdown vin gnd oscillator zero-cross sensing bleeding fet *no te bandgap scp + en shutdown 100 vref2 vref3 *note: for fixed output options only figure 22. functional block diagram note: for adjustable output version, the internal feedback resistor divider is disabled and the fb pin is directly connected to the error amplifier. isl9103, isl9103a
10 fn6828.2 november 24, 2009 the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage control loop. the feedback signal comes from the fb pin. the soft-start block only affects the operation during the start-up and will be discussed separately in ?soft-start? on page 11. the eamp is a transconductance amplifier, which converts the voltage error signal to a current output. the voltage loop is internally compensated by a rc network. the maximum eamp voltage output is precisely clamped to the bandgap voltage. skip mode (pfm mode) under light load condition, isl9103, isl9103a automatically enters a pulse-skipping mode to minimize the switching loss by reducing the switching frequency. figure 24 illustrates the skip mode operation. a zero-cross sensing circuit (as shown in figure 22) monitors the current flowing through sw node for zero crossing. when it is detected to cross zero for 16-consecutive cycles, the regu lator enters the skip mode. during the 16-consecutive cycles , the inductor current could be negative. the counter is reset to zero when the sensed current flowing through sw node does not cross zero during any cycle within the 16-consecutive cycles. once isl9103, isl9103a enters the skip mode, the pulse modulation starts being controlled by the skip comparator shown in figure 22. each pulse cycle is still synchr onized by the pwm clock. the p-channel mosfet is turned on at the rising edge of clock and turned off when its current reaches ~20% of the peak current limit. as the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. when the output voltage is sensed to reach 1.5% above its nominal voltage, the p-channel mosfet is turned off immediately and the inductor current is fully discharged to zero and stays at zero. the output voltage reduces grad ually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-channel mosfet will be turned on again, repeating the previous operations. the regulator resumes normal pwm mode operation when the output voltage is sensed to drop below 1.5% of its nominal voltage value. enable the enable (en) pin allows user to enable or disable the converter for purposes such as power-up sequencing. with en pin pulled to high, the converter is enabled and the internal reference circuit wakes up first and then the soft start-up begins. when en pin is pulled to logic low, the converter is disabled, both p-channel mosfet and n-channel mosfets are turned off, and the output capacitor is discharged through internal discharge path. figure 23. pwm operation waveforms v eamp d i l v out v csa 16 cycles clock i l v out 0 v out_nominal 20% peak current limit 1.015*v out_nominal figure 24. skip mode operation waveforms isl9103, isl9103a
11 fn6828.2 november 24, 2009 overcurrent protection the overcurrent protection is provided on isl9103, isl9103a when overload condition happens. it is realized by monitoring the csa output with the ocp comparator, as shown in figure 22. when the current at p-channel mosfet is sensed to reach the current limit, the ocp comparator is triggered to turn off the p-channel mosfet immediately. short-circuit protection isl9103, isl9103a has a short-circuit protection (scp) comparator, which monitors the fb pin voltage for output short-circuit protection. when t he output voltage is sensed to be lower than a certain threshold, the scp comparator reduces the pwm oscillator frequency to a much lower frequency to protect the ic from being damaged. undervoltage lockout (uvlo) when the input voltage is below the undervoltage lock out (uvlo) threshold, isl9103, isl9103a is disabled. soft-start the soft-start feature eliminates the inrush current during the circuit start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. low dropout operation the isl9103, isl9103a features low dropout operation to maximize the battery life. when the input voltage drops to a level that isl9103, isl9103a can no longer operate under switching regulation to maintain the output voltage, the p-channel mosfet is completely turned on (100% duty cycle). the dropout voltage under such condition is the product of the load current and the on-resistance of the p-channel mosfet. minimum required input voltage v in under this condition is the su m of output voltage plus the voltage drop cross the inductor and the p-channel mosfet switch. thermal shut down the isl9103, isl9103a provides built-in thermal protection function. the thermal shutdown threshold temperature is +130c (typ) with a 30c (typ) hysteresis. when the internal temperature is sensed to r each +130c, the regulator is completely shut down and as the temperature drops to +100c (typ), the isl9103, isl9103a resumes operation starting from the soft-start. applications information inductor and output capacitor selection to achieve better steady state and transient response, isl9103, isl9103a typically uses a 2.2h inductor. the peak-to-peak inductor current ripple can be expressed in equation 1: in equation 1, usually the typical values can be used but to have a more conservative estimation, the inductance should consider the value with worst case tolerance; and for switching frequency f s , the minimum f s from the ?electrical specifications? table on page 3 can be used. to select the inductor, its satura tion current rating should be at least higher than the sum of the maximum output current and half of the delta calculat ed from equation 1. another more conservative approach is to select the inductor with the current rating higher than t he p-channel mosfet peak current limit. another consideration is the inductor dc resistance since it directly affects the efficiency of the converter. ideally, the inductor with the lower dc resistance should be considered to achieve higher efficiency. inductor specifications could be different from different manufacturers so please che ck with each manufacturer if additional information is needed. for the output capacitor, a ceramic capacitor can be used because of the low esr values, which helps to minimize the output voltage ripple. a typical value of 10f ceramic capacitor should be enough for most of the applications and the capacitor should be x5r or x7r. input capacitor selection the main function for the input capacitor is to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switchin g current from flowing back to the battery rail. a 10f ceramic capacitor (x5r or x7r) is a good starting point for the input capacitor selection. output voltage setting resistor selection for isl9103, isl9103a adjustable output option, the voltage resistors, r 1 and r 2 , as shown in figure 21, set the desired output voltage values. the output voltage can be calculated using equation 2: where v fb is the feedback voltage (typ ically it is 0.8v). the current flowing through the voltage divider resistors can be calculated as v o /(r 1 + r 2 ), so larger resistance is desirable to minimize this current. on the other hand, the fb pin has leakage current that will cause error in the output voltage setting. the leakage current has a typical value of 0.1a. to minimize the accuracy impact on the output voltage, select the r 2 no larger than 200k . i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) v o v fb 1 r 1 r 2 ------ - + ?? ?? ?? ? = (eq. 2) isl9103, isl9103a
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6828.2 november 24, 2009 for adjustable output versions, c3 (shown in figure 21) is highly recommended for improving stability and achieving better transient response. table 2 provides the recommended component values for some output voltage options. layout recommendation the pcb layout is a very important converter design step to make sure the designed converter works well, especially under the high current high switching frequency condition. for isl9103, isl9103a, the power loop is composed of the output inductor l, the output capacitor c out , the sw pin and the pgnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide; the same type of traces should be used to connect the vin pin, the input capacitor c in and its ground. the switching node of the converter, the sw pin, and the traces connected to this node are very noisy, so keep the voltage feedback trace and ot her noise sensitive traces away from these noisy traces. the input capacitor should be placed as close as possible to the vin pin. the ground of the input and output capacitors should be connected as close as possible as well. in addition, a solid ground plane is helpful for emi performance. table 2. recommended isl9103, isl9103a adjustable output version circuit configuration vs v out vout (v) l ( h ) c2 ( f) r1 (k ) c3 (pf) r2 (k ) 0.8 2.2 10 0 n/a n/a 1.0 2.2 10 44.2 100 178 1.2 2.2 10 80.6 47 162 1.5 2.2 10 84.5 47 97.6 1.8 2.2 10 100 47 80.6 2.5 2.2 10 100 47 47.5 2.8 2.2 10 100 47 40.2 3.3 2.2 10 102 47 32.4 isl9103, isl9103a
13 fn6828.2 november 24, 2009 isl9103, isl9103a package outline drawing l6.1.6x1.6 6 lead ultra thin dual flat no-l ead col plastic package (utdfn col) rev 1, 11/07 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 1.60 5x 0 . 40 0 . 1 0.15 ( 1 . 4 ) (4x) ( 6x 0 . 25 ) ( 1x 0 .70 ) ( 4x 0 . 5 ) 0 . 55 max base plane c seating plane 0.08 c 0.10 c 0.25 +0.05 / -0.07 see detail "x" 0.10 4 ca mb index area 6 pin 1 1.60 a b pin #1 index area 0.50 2x 1.00 4x 6 ( 5x 0 . 60 ) 0 . 00 min. 0 . 05 max. c 0 . 2 ref 4 3 6 1 1x 0.5 0.1

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